1. Field of the Invention
The present invention relates to a semiconductor memory device using dynamic type memory cells and more particularly to a dynamic RAM (DRAM).
2. Description of the Related Art
A DRAM having a one-transistor-one-capacitor memory cell structure is notably progressing in degree of integration in accordance with an improvement in memory cell structure and an advance of fine processing technique. Conventionally, equal to or more than double-layered polysilicon film is employed to form capacitor and transfer gate of a memory cell.
FIG. 1 is a circuit diagram of a conventional general-purpose DRAM, and FIG. 2A is a plan view showing the element structure of the DRAM, while FIG. 2B is a cross-sectional view taken along line 2B-2B of FIG. 2A.
FIGS. 2A and 2B illustrate a semiconductor substrate 1, source and drain diffusion layers 2 of a MOS transistor, word lines 3 each constituted of a polysilicon layer and serving as a gate of the MOS transistor, storage node electrodes 4a each constituted of a polysilicon layer and connected to one of the source and drain diffusion layers and serving as part of a capacitor, plate electrodes 4b each formed of a polysilicon layer and provided on the storage node electrodes with a capacitor insulating film therebetween, an element isolation region 5, and bit lines 6 each connected to the other of the source and drain diffusion layers and formed of wiring metal such as aluminum. As shown in FIG. 2A, the plate electrodes 4b have a plurality of openings 7 through which the bit lines 6 contact the electrodes 4b. In FIG. 2A, the areas surrounded with broken lines are element regions 9.
The above DRAM has a large cell area of 8F.sup.2, and has a disadvantage that the number of steps of manufacturing is increased since three-layered polysilicon layer is used, and element isolation is performed by LOCOS (Local Oxidation of Silicon).
In addition, in the circuit arrangement shown in FIG. 1, data of a cell selected by a word line connected to a bit line BL is compared with a reference potential of a dummy cell connected to a bit line BL in a sense amplifier S/A. When the reference potential is Vcc/2, even if data is either "H" or "L", a difference in potential between bit lines after the data is read out is expressed as follows: EQU (Vcc/2.multidot.Cs)/(CB+Cs)
Therefore, since a sufficient cell capacitance Cs cannot be secured due to an increase in bit line capacitance CB and miniaturization of memory cells, the potential difference tends to decrease more and more, and it is thus very important to secure and increase the amplitude of a signal to be read out.
As described above, the conventional DRAM has the following drawbacks. Because of miniaturization of memory cells, the cell capacitance Cs cannot be secured sufficiently, resulting in decrease in noise margin and reliability. Furthermore, the manufacturing steps are increased in number.